March 30, 2026 Co-packaged Optics and and Quantum Intelligence Newsletter
A Strategic Focus on Assembly and Test for Advanced Packaging in CPO and Quantum Devices
Photonics & Quantum Intelligence
Teradyne Launches Photon 100 — First Purpose-Built High-Volume Opto-Electric ATE Platform for SiPh and CPO Manufacturing
At OFC 2026, Teradyne (NASDAQ: TER) launched the Photon 100, a comprehensive opto-electric automated test platform purpose-built for high-volume silicon photonics and co-packaged optics manufacturing. The platform integrates optical and electrical instrumentation directly into Teradyne's proven UltraFLEXplus ATE platform — the same platform that already dominates the semiconductor ATE market — enabling high-throughput automated testing across all key manufacturing stages in a single integrated system. Specifically, the Photon 100 supports wafer-level test (single-sided and double-sided), optical engine test, and co-packaged module test insertions, covering the complete CPO production flow from first silicon to finished module. The platform is designed to allow customers to tailor optical instrumentation configurations and select preferred ecosystem partners for wafer-level and die-level probing, which means it is ATE-platform-centric rather than optical-head-proprietary — a deliberate architectural choice that mirrors how Teradyne has historically expanded into new semiconductor test markets. Geeta Athalye, VP of Silicon Photonics Test at Teradyne, described the Photon 100 as delivering "seamless performance at scale today and the flexibility to evolve alongside our customers' needs as the industry continues to innovate."
This is the most significant single equipment announcement in the CPO test space since Teradyne's earlier ficonTEC partnership (high-volume double-sided SiPh wafer probe, announced March 2025). The Photon 100 represents Teradyne asserting a standalone CPO test platform identity — not just a plug-in module for the ficonTEC workflow — which signals a strategic decision to own the CPO test platform layer, not just the ATE electrical core. The framing — "operational simplicity," "eliminate multi-vendor integration burden," "built and maintained by Teradyne" — is a direct competitive statement against the fragmented multi-vendor test cell architecture that is currently the industry norm for CPO production test. In a market where the dominant CPO test approach today is still custom-assembled from disparate ATE, optical probing, and fiber attach components, a single-vendor integrated platform from the world's largest semiconductor ATE company is a structural market shift.
The Photon 100 defines the competitive baseline for any new CPO test cell entrant. Its three key differentiators — UltraFLEXplus integration, wafer-through-module coverage in one platform, and single-vendor operational simplicity — are precisely the gaps that a new entrant with active optical alignment capability, US manufacturing presence, and applications engineering depth could address at the CPO module level, where Teradyne's pure ATE heritage has less natural advantage. The OFC 2026 launch timing was deliberate: it positions Teradyne as the test infrastructure layer for the NVIDIA CPO production ramp. Any new entrant must now define their position relative to Teradyne Photon 100, not around it.
OFC 2026 Post-Show Analysis: CPO Has Crossed Its Reliability Threshold — Meta's 90 Million Hours and the Shift to System-Level Competition
Post-OFC 2026 analysis from SemiVision Research and CableLabs has crystallised the event's signal more sharply than the show-floor announcements alone conveyed. The single most important data point from OFC 2026 — which received less coverage than the product launches — was Meta's presentation of 90 million flap-free CPO port hours. This figure, reported at OFC's technical sessions, represents a 90-fold increase over the 1 million port-hour milestone Broadcom announced in October 2025 at ECOC. It was presented as a field characterisation result, not a controlled lab environment test. The practical interpretation: CPO has now accumulated sufficient production-equivalent operational hours at a hyperscaler running live AI workloads to answer the reliability question definitively. SemiVision's analysis characterised this as "Meta has answered the hardest question around CPO: reliability."
The second structural signal from OFC 2026 post-analysis is the emergence of what CableLabs characterised as three new MSA-level interoperability frameworks addressing different tiers of the interconnect stack simultaneously: the OCI (Optical Compute Interconnect) MSA for open scale-up optical interconnect wavelength and modulation standards; the Open CPX MSA for socketed optical engine interoperability at the co-packaged and near-package interface; and the XPO MSA for 12.8T liquid-cooled pluggable optics. The concurrent emergence of three distinct MSA frameworks at the same conference signals that the industry has passed the phase where a single proprietary architecture can capture the whole CPO market — and entered a phase where interoperability specifications enable parallel, competing supply chains for different deployment scenarios. The SemiVision analysis frames NVIDIA (microring COUPE CPO), Lightmatter (in-package DWDM 3D interposer), and Broadcom (system-level CPO platform) as representing "three different futures" for CPO architecture — all simultaneously viable for different portions of the AI interconnect landscape.
Meta's 90 million-hour result is the most important CPO test infrastructure signal in the period. It means that the reliability qualification bar for CPO has moved from controlled lab demonstration to live production validation at hyperscale. Test equipment vendors serving CPO production lines must now be capable of certifying systems to production-level thermal cycling and link stability specifications that are validated against the Meta/Broadcom operational dataset — not just against internal engineering specifications. The three-MSA architecture landscape means test cell designs must be reconfigurable across COUPE-bonded, socketed CPX, and pluggable XPO form factors rather than being optimised for a single interface standard.
Post-GTC 2026: Taiwan CPO Packaging Supply Chain Mobilises on Confirmed Production Scale — Thousands of CPO Racks Per Week Now Manufacturing
Jensen Huang's confirmation at GTC 2026 that NVIDIA CPO-equipped racks are being manufactured at thousands per week has triggered active supply chain mobilisation across Taiwan's electronics manufacturing ecosystem. Digitimes reported that Taiwanese firms are "preparing for silicon photonics and CPO packaging opportunities as AI data center continues growth," with Sunengine Technology entering the CPO advanced packaging supply chain as a direct response to the GTC 2026 production confirmation. The implication — that CPO rack assembly has moved from qualification production to volume production within the NVIDIA supply chain — means that every tier of the CPO packaging supply chain is now facing real capacity planning decisions, not speculative roadmap positioning.
The broader post-GTC supply chain picture from analyst commentary: NVIDIA's dual copper-optical strategy (confirmed explicitly by Huang: "We need a lot more capacity for copper. We need a lot more capacity for optics. We need a lot more capacity for CPO.") means the capacity signal is unambiguous and large. Taiwan's OSAT and advanced packaging ecosystem — SPIL, ASE, Foxconn, Fabrinet, and now Sunengine — is the primary assembly layer for CPO modules feeding into NVIDIA's Spectrum-X and Quantum-X platforms. The AWS commitment of over one million NVIDIA GPUs across Blackwell, Rubin, and Groq platforms establishes a defined demand floor that makes CPO capacity expansion a straightforward business decision for any supplier already in the NVIDIA ecosystem.
The shift from qualification to volume production in NVIDIA's CPO supply chain is the equipment procurement trigger. OSATs and module assemblers who commit to CPO capacity now are ordering equipment for delivery in 6–18 months to support Vera Rubin Ultra and Feynman ramp schedules. The window for a new assembly and test equipment entrant to be qualified on the production line for the Rubin Ultra and Feynman cycles is approximately now through mid-2027. After that window, existing qualified equipment vendors will have incumbent advantages that are very difficult to displace in a production environment.
OCI MSA Emerges at OFC 2026 — Optical Compute Interconnect Standard Targets Open Scale-Up Interconnect for AI Clusters
Separate from the Open CPX MSA and XPO MSA covered in Edition 2, a third new multi-source agreement — the OCI (Optical Compute Interconnect) MSA — was active at OFC 2026 and represents the most architecturally ambitious of the three. The OCI MSA defines wavelengths and modulation formats for an open optical scale-up interconnect designed for AI clusters — directly targeting the application space that NVIDIA's NVLink8 CPO will occupy in 2028, but as an open, multi-vendor standard rather than a proprietary NVIDIA platform. The OCI architecture is distinguished from switch-oriented CPO (Spectrum-X/Quantum-X) in that it targets processor-to-processor scale-up interconnect — the innermost, lowest-latency tier of AI factory interconnect — using DWDM wavelength division multiplexing to carry data between XPUs within and across racks. Intel has been a key driver of the OCI concept through its own Optical Compute Interconnect chiplet program (4 Tbps, 5 pJ/bit, demonstrated at OFC 2024 co-packaged with an Intel CPU); the OCI MSA extends this into an open ecosystem standard.
The significance for the CPO competitive landscape: if the OCI MSA succeeds in establishing an open standard for XPU-to-XPU optical scale-up interconnect, it would create a second market tier for CPO alongside the switch CPO market. XPU-to-XPU optical interconnect is a larger total addressable market than switch CPO (every XPU needs it, not just every switch), and an open MSA standard would enable a multi-vendor supply chain for CPO optical engines at the XPU package level — exactly the market that Ayar Labs (TeraPHY + UCIe optical chiplet), Lightmatter (Passage L200 3D CPO), and Intel (OCI chiplet) are each pursuing through their own proprietary approaches. The OCI MSA attempts to standardise the interface so that multiple vendors' optical engines can compete on a common platform specification.
XPU-level optical scale-up interconnect requires a different test insertion than switch CPO. The latency, jitter, and BER specifications for XPU-to-XPU optical links are substantially more stringent than for switch links — these are synchronisation-critical paths in AI training clusters where nanosecond-level jitter differentials affect model convergence. The OCI MSA's wavelength and modulation format specifications, once published, will define the next generation of optical engine test requirements for XPU package-level CPO. Equipment vendors who begin developing OCI-compliant test capabilities now — before the MSA is fully ratified — will be positioned ahead of the market when XPU CPO enters production qualification (estimated 2027–2028 for early deployments).
IonQ Acquires SkyWater Technology for $1.8B — First Vertically Integrated Quantum Platform with In-House US Foundry
On January 26, 2026, IonQ (NYSE: IONQ) announced a definitive agreement to acquire SkyWater Technology (NASDAQ: SKYT), the largest exclusively US-based pure-play semiconductor foundry, in a cash-and-stock transaction valued at approximately $1.8 billion ($35 per share, a 38% premium). SkyWater operates fabrication facilities in Bloomington, Minnesota; Florida; and Texas, serving aerospace and defense, commercial semiconductor, and advanced technology customers. It is designated a "trusted foundry" by the US Department of Defense, giving it cleared access to defense programs with stringent supply chain requirements. The transaction is expected to close by the end of September 2026 pending regulatory and shareholder approvals. SkyWater will operate as a wholly owned subsidiary under its existing name, led by CEO Thomas Sonderman, and will continue to serve commercial and government customers as a merchant semiconductor foundry. IonQ's CEO Niccolo de Masi called it "the final piece — semiconductors — to IonQ's existing US-based manufacturing," creating "the world's only full-stack quantum platform company" with secure US design, packaging, and chip fabrication end-to-end.
The strategic rationale is explicitly tied to manufacturing scale rather than near-term product. IonQ's stated roadmap target — 200,000 physical qubit QPUs enabling 8,000 ultra-high fidelity logical qubits, with functional testing expected to begin in 2028 — is a manufacturing problem, not a physics problem. Achieving that at yield requires semiconductor-grade process control, repeatability, and failure mode analysis that is currently impossible to achieve through external foundry relationships alone. SkyWater's process modules for quantum devices (superconducting qubits, ion trap chips, quantum sensing) — along with its advanced packaging capabilities and existing relationships with DOE national labs and defense programs — make it the most credible domestic quantum foundry asset available. Futurum Research characterised the deal as "aligning quantum system development with established semiconductor operating models," noting that IonQ's 2028 physical qubit targets "are manufacturing variables." SkyWater projected approximately $600 million in 2026 revenue as a standalone company, immediately bulking up IonQ's combined entity profile ahead of its IPO window.
SkyWater's Minnesota, Florida, and Texas facilities will become Regional Quantum Production Hubs under the combined entity. This is directly material to any company considering US-based quantum manufacturing partnerships or equipment supply: SkyWater is now IonQ's captive foundry, but it remains a merchant supplier to third parties. For assembly and test equipment vendors, SkyWater's expanded quantum manufacturing mandate means the facilities will require quantum-specific process equipment and test infrastructure at volumes higher than any US quantum foundry has previously operated. The Florida facility in particular — already serving quantum programs at NASA, defense, and commercial customers — is likely to see the earliest quantum-specific capital equipment procurement driven by IonQ's roadmap.
IonQ Reports $130M FY2025 Revenue — First Quantum Company to Exceed $100M Annual GAAP Revenue, 202% Year-over-Year Growth
On February 25, 2026, IonQ reported its full-year 2025 financial results: $130 million in GAAP revenue, a 202% year-over-year increase that beat the company's own guidance midpoint by 20%. Q4 2025 alone contributed $61.9 million (429% year-over-year growth, 55% above guidance midpoint). IonQ ended the year with $3.3 billion in cash, cash equivalents, and investments — the most financial runway of any pure-play quantum hardware company globally. More than 60% of 2025 revenue came from commercial customers (versus government contracts), and approximately 30% from international markets — a revenue composition that validates commercial traction beyond the government programs that have historically driven quantum hardware revenue. IonQ's 2026 guidance projects $235 million at the guidance midpoint, which would represent roughly 80% year-over-year growth. Net income of $753.7 million and GAAP EPS of $2.13 in Q4 2025 were driven substantially by non-cash gains, but the operating trajectory is unambiguously positive. IonQ CEO Niccolo de Masi described the year as "a strategic and financial inflection point."
The $100M GAAP revenue threshold is the first in the quantum hardware sector and represents a structural market milestone, not just an IonQ metric. It demonstrates that quantum computing has progressed from a purely government-funded research programme to a commercially viable product with enterprise customers paying recurring subscription and service fees for access to quantum systems. The 2026 guidance of $235M (midpoint) implies the commercial traction is durable, not a one-time contract event. In context with the SkyWater acquisition — which adds approximately $600M in annual revenue from SkyWater's existing semiconductor foundry business — the combined IonQ entity is on a trajectory toward $800M+ combined revenue by late 2026, creating a substantially different financial profile than any other quantum hardware company and positioning the eventual Quantinuum IPO comparison as the key benchmarking event for sector valuation.
IonQ's $3.3 billion cash position, combined with $235M projected 2026 revenue and the SkyWater acquisition, creates the financial foundation for substantial quantum manufacturing capital equipment procurement in 2026–2028. The SkyWater integration will require investment in quantum-specific process equipment at the foundry level. Companies positioned to supply assembly, packaging, characterisation, and test infrastructure to a well-capitalised, vertically integrated US quantum platform company have a clear procurement pathway that did not exist at this scale twelve months ago.
Quantinuum Achieves 48 Error-Corrected Logical Qubits from 98 Physical Qubits on Helios — Beyond-Break-Even at 2:1 Physical-to-Logical Ratio
On March 14, 2026, Quantinuum announced the implementation of high-rate Iceberg codes on its 98-qubit Helios trapped-ion processor, achieving a result widely described as years ahead of schedule: 48 fully error-corrected logical qubits and 94 error-detected logical qubits from just 98 physical qubits. The physical-to-logical qubit ratio of approximately 2:1 for full error correction — achieved through code concatenation (two layers of Iceberg codes nested together) — was previously considered unattainable at this fidelity. For comparison, surface code approaches require roughly 100 physical qubits per logical qubit at equivalent error rates, meaning a comparable result via surface code would have required approximately 4,800 physical qubits. Logical gate error rates of roughly 1 in 10,000 operations (10⁻⁴ per cycle) were achieved, approximately 3x better than the raw physical qubit error rate — confirming "beyond break-even" performance where error-corrected logical qubits outperform unprotected physical qubits. A 94-logical-qubit GHZ entangled state was generated with 94.9% fidelity, and a partially fault-tolerant quantum simulation of the 3D XY model of quantum magnetism was executed on 64 error-detected logical qubits — the largest encoded quantum magnetism simulation to date. Quantinuum stated "we are officially entering the era of large-scale logical computing."
The result is enabled by two architectural properties of the Helios QCCD (Quantum Charge-Coupled Device) platform that are unique among commercial quantum systems: all-to-all qubit connectivity (via ion transport through an ion junction, enabling non-local interactions required by Iceberg codes) and barium-ion qubits (enabling leakage error detection at the atomic level). The Iceberg code approach is specifically suited to systems with flexible, all-to-all connectivity — architectures that fixed-layout superconducting systems (IBM, Google) cannot directly replicate. Quantinuum is packaging the Iceberg code result into QCorrect, an upcoming developer tool that will allow users to automatically apply Iceberg-style encoding to their own quantum circuits on Helios. Real-time error decoding on NVIDIA Grace Hopper GPUs (via NVQLink) is integrated into the Helios stack, treating error correction as a dynamic computational process rather than a post-processing step. This NVIDIA/Quantinuum integration is the most concrete demonstration to date of the quantum-GPU hybrid computing architecture that NVIDIA has been building toward through its NVQLink and CUDA-Q investments.
The 2:1 physical-to-logical qubit ratio result changes the engineering economics of fault-tolerant quantum computing in a concrete way: the physical qubit counts required to reach commercially useful logical qubit thresholds drop by a factor of 50 or more compared to surface code projections. This directly affects the scale of quantum chip fabrication, packaging, and test required per logical qubit — and therefore the capital equipment procurement profile for the path to fault-tolerant systems. If Iceberg-class codes scale with Helios' successor processors, the quantum chip manufacturing infrastructure required for 1,000 reliable logical qubits may be buildable at physical qubit counts of 2,000–5,000 rather than 100,000–500,000 — a different capital intensity order of magnitude. Assembly and test vendors planning quantum equipment roadmaps should model both surface-code-scale (high physical qubit count, low encoding efficiency) and Iceberg-scale (low physical qubit count, high encoding efficiency) scenarios.
Quantinuum Establishes Singapore R&D Centre — First Helios Deployment Outside US Planned for 2026; CFO Appointment Signals IPO Preparation
On March 11, 2026, Quantinuum announced the establishment of an R&D and Operations Centre in Singapore — its first physical expansion outside the United States — with a commitment to deploy the Helios quantum computer in Singapore later in 2026. The centre is supported by Singapore's Economic Development Board and backed by a strategic partnership with Singapore's National Quantum Office and National Quantum Computing Hub. Singapore's Prime Minister Lawrence Wong cited Quantinuum by name in his national budget speech, characterising Helios as a system that will enable Singaporean researchers and companies to work on "meaningful projects" in pharmaceutical simulation, financial modelling, and materials science. The centre will serve Quantinuum's partnership with the National Quantum Computing Hub, which is part of Singapore's broader National Quantum Strategy managed through A*STAR.
On March 18, 2026, Quantinuum separately announced the appointment of Nitesh Sharan as Chief Financial Officer, effective April 6, 2026. Sharan comes from SoundHound AI, where he led the company through its 2022 public listing and oversaw financial planning and capital market strategy. The appointment of a CFO with recent IPO execution experience — specifically someone who has led a technology company through a public offering — is the clearest signal yet of the timeline seriousness behind Quantinuum's January 2026 confidential S-1 submission. Taken together with the Singapore expansion (international commercial revenue diversification), the Helios Iceberg QEC result (technology leadership narrative), and the $10B pre-money S-1 target, Quantinuum is in active IPO preparation with a credible 2026–2027 window.
The Singapore deployment is the first commercial Helios installation outside of Quantinuum's US facilities (Broomfield, CO and Cambridge, UK). Each Helios installation requires cryogenic infrastructure, precision vacuum packaging, trap chip integration, and calibration at system level — a deployment process that represents the earliest signal of what international quantum hardware logistics and service infrastructure will require. Singapore's National Quantum Computing Hub is explicitly structured to evaluate quantum hardware for national computing infrastructure, making it analogous in function to the UK's ProQure programme. An IPO at $10B+ valuation would provide capital for substantial hardware manufacturing scale-up, with direct equipment procurement implications in the 2027–2028 window.
NVIDIA Unveils NVQLink Open Architecture at GTC 2026 — Quantum-GPU Hybrid Computing Becomes a Product, Not a Research Initiative
At GTC 2026 on March 16, NVIDIA formally unveiled NVQLink — an open system architecture for connecting quantum processors to NVIDIA GPU systems — alongside a new dedicated quantum computing research laboratory planned for Boston. Jensen Huang stated the Boston lab "will likely be the most advanced accelerated computing, hybrid quantum computing research lab in the world," to be built in collaboration with Harvard University and MIT. NVQLink is an open interconnect specification that allows QPUs from multiple vendors to attach to NVIDIA's GPU computing fabric, treating quantum processors as specialised co-processors within a classical-quantum hybrid compute stack. IonQ and KISTI (Korea Institute of Science and Technology Information) announced a partnership on March 17 at GTC 2026 to build South Korea's sovereign Quantum-HPC ecosystem using IonQ's trapped-ion hardware connected to KISTI's national supercomputing backbone via NVIDIA NVQLink. Quantinuum's Helios platform already integrates NVIDIA Grace Hopper GPUs via NVQLink for real-time quantum error decoding, and this is now the production architecture shipping to commercial customers. PNNL (Pacific Northwest National Laboratory) announced open-source GPU acceleration for quantum computing via NVIDIA NVQLink at GTC 2026, extending NVQLink's reach into the national laboratory ecosystem.
The NVQLink announcement is architecturally significant because it standardises the quantum-GPU interface in a way that positions NVIDIA as the classical computing substrate for commercial quantum deployment — regardless of which qubit modality (trapped ion, neutral atom, photonic, superconducting) wins the hardware race. Every quantum hardware vendor who integrates NVQLink gains access to the GPU-accelerated decoding, simulation, and hybrid algorithm infrastructure that NVIDIA has built. Every NVIDIA GPU customer who deploys NVQLink-connected QPUs generates demand for quantum hardware. The Boston quantum research lab further cements NVIDIA's role as the infrastructure layer connecting classical AI compute and quantum compute — a position analogous to how NVIDIA became the infrastructure layer connecting CPU and GPU compute through CUDA in the 2007–2012 period.
NVQLink deployments require quantum hardware to be integrated with GPU compute racks — creating new co-packaging and interconnect requirements at the system level (QPU to GPU communication over optical or electrical links at cryogenic-to-room-temperature boundaries). The IonQ/KISTI and Quantinuum/Helios NVQLink deployments are the first commercial instances of this architecture at national infrastructure scale. Equipment vendors who can support the mechanical, thermal, and electrical co-integration requirements of QPU-GPU hybrid systems — particularly the cryogenic-to-room-temperature packaging boundary — are addressing a new system-level requirement that is just beginning to emerge as a distinct product category.