March 11, 2026 Co-packaged Optics and and Quantum Intelligence Newsletter
A Strategic Focus on Assembly and Test for Advanced Packaging in CPO and Quantum Devices
Photonics & Quantum
Intelligence
OFC 2026 Opens Next Week in Los Angeles — Largest Exhibition to Date
The Optical Fiber Communication Conference (March 15–19, 2026, Los Angeles Convention Center) is sold out across its exhibition floor, with 700+ exhibiting companies and 16,000 expected attendees from 90 countries. AI-driven bandwidth demand is the defining theme. Key CPO-related exhibitor commitments already confirmed include:
- STMicroelectronics — presenting its newly ramped PIC100 silicon photonics platform and roadmap for PIC100 TSV, targeting NPO and CPO at 800G/1.6T.
- Tower Semiconductor — showcasing SiPho and SiGe BiCMOS platforms for CPO scale-up, DWDM lasers, and optical circuit switching.
- Ayar Labs + Wiwynn — unveiling a rack-scale reference design capable of integrating 1,024 GPUs via optical interconnects, targeting 100–200 kW per rack vs. 600+ kW for copper-based alternatives.
- OIF — multi-vendor interop demo with 40 member companies covering CEI-224G, live 448G, CMIS, and co-packaging building blocks.
- Semtech — new 224G-per-lane TIA and MZM driver family for 800G, 1.6T, and 3.2T linear optical interconnects.
- CEA-Leti + NcodiN — strategic collaboration announcement to industrialize optical interposer technology on 300 mm photonics process for AI chips.
- LightSpeed Photonics — launching what it describes as the industry's first solderable near-packaged optical interconnect technology, positioned between CPO and LPO.
Full post-OFC wrap will appear in Edition 2, after March 19.
NVIDIA GTC 2026 Opens March 16 — Silicon Photonics and Rubin Ultra in Focus
NVIDIA's GTC 2026 runs March 16–19, 2026 at the SAP Center in San Jose, with 30,000 attendees from 190 countries. CEO Jensen Huang's keynote (March 16, 11 a.m. PT) is expected to cover the full stack: chips, software, models, and applications. Pre-conference reporting from DigiTimes and others points to three CPO-relevant themes for Vernon's sector:
- Silicon photonics ramp — GTC is expected to feature updates on NVIDIA's Spectrum-X Photonics and Quantum-X Photonics switch platforms (both using TSMC COUPE), with Rubin Ultra expected to deepen the optical interconnect narrative for 2026–2027 volume ramps.
- CPO supply chain acceleration — Taiwan-based suppliers including Poloniex and Boruwei (Poroway) are ramping for NVIDIA's Rubin Ultra cycle; shipment projections for CPO-enabled modules suggest 137% annual output growth.
- Scale-up interconnect — with Marvell's Celestial AI acquisition and Ayar Labs' ecosystem moves, GTC is likely to surface competitive positioning across the NVLink vs. UALink/Ethernet CPO ecosystem divide.
Full post-GTC analysis will appear in Edition 2, after March 19.
NVIDIA Invests $4 Billion in Coherent and Lumentum — Largest Single Capital Commitment to Silicon Photonics Supply Chain
On March 2, 2026, NVIDIA announced strategic investments of $2 billion each in Coherent (NYSE: COHR) and Lumentum (NASDAQ: LITE), two of the largest publicly traded photonics companies and existing suppliers to NVIDIA's Spectrum-X CPO switch platform. Each deal is structured as a non-exclusive, multi-year strategic agreement combining an equity investment with a multi-billion dollar purchase commitment from NVIDIA and future capacity access rights — for advanced laser components in the case of Lumentum, and for advanced laser and optical networking products in the case of Coherent. Lumentum will use the investment to support R&D and manufacturing expansion in the US, including a new fabrication facility. Coherent will deploy proceeds toward R&D, future capacity, and its existing US manufacturing footprint. Both companies are already embedded in NVIDIA's Spectrum-X supply chain: Lumentum provides lasers and Coherent collaborates on silicon photonics.
Jensen Huang's framing was unambiguous: "Together with Lumentum, NVIDIA is advancing the world's most sophisticated silicon photonics to build the next generation of gigawatt-scale AI factories." The $4 billion total is the largest single capital commitment to the silicon photonics supply chain in the sector's history. The timing — immediately before GTC 2026 and OFC 2026 — amplified signal strength considerably. For context, Lumentum's valuation had already increased roughly tenfold over the preceding year; Coherent's had more than quadrupled. NVIDIA has not yet announced CPO adoption for its NVLink scale-up interconnect; the investments in Lumentum and Coherent are widely read as preparatory positioning for that transition, potentially on a Rubin Ultra or successor platform timeline.
Lumentum's commitment to build a new US fabrication facility is the most direct equipment market implication. A greenfield or expanded InP laser fab requires wafer fabrication tools, die attach, hermetic packaging, and burn-in test infrastructure specific to III-V laser manufacturing — a distinct and underserved equipment segment relative to silicon photonics. For assembly and test vendors with III-V capability, this is a significant capital equipment pipeline signal with a 2–4 year horizon.
NVIDIA Unveils Spectrum-X and Quantum-X CPO Switches at GTC 2025 — World's First 1.6 Tb/s Co-Packaged Optics on TSMC COUPE
On March 18, 2025, NVIDIA CEO Jensen Huang introduced the world's first commercial co-packaged optics networking platforms at GTC 2025: Spectrum-X Photonics (Ethernet) and Quantum-X Photonics (InfiniBand). Both are built on TSMC's COUPE platform using micro ring modulator (MRM) technology — a departure from conventional Mach-Zehnder pluggables. Huang called it "really crazy, crazy technology." The Quantum-X Photonics switch delivers 144 ports at 800 Gb/s InfiniBand (115.2 Tb/s aggregate), with each module housing a Quantum-X800 ASIC (107B transistors on TSMC 4N) plus 18 silicon photonic engines, 36 laser inputs, and 324 optical connections in a liquid-cooled package. The Spectrum-X Photonics Ethernet platform scales from 128×800G (100 Tb/s) to 512×800G (409.6 Tb/s). Versus conventional pluggables: 3.5x power efficiency improvement, 63x greater signal integrity, 10x better network resiliency, 4x fewer lasers. Quantum-X Photonics InfiniBand switches shipped 2H 2025; Spectrum-X Photonics Ethernet is on schedule for 2026.
The supply chain named at launch defined the CPO ecosystem: TSMC (COUPE foundry), Lumentum (lasers for Spectrum-X), Coherent (CPO co-development), Corning (fiber), Foxconn (assembly), Senko (connectors), Browave, SPIL, Sumitomo Electric, TFC, and Fabrinet. This announcement transformed CPO from roadmap item to shipping product with a named supply chain and performance specifications. LightCounting's post-GTC analysis confirmed InfiniBand CPO arrival in 2H 2025 and Ethernet CPO in 2H 2026, and framed 2028 as the horizon for NVLink scale-up CPO adoption — the next major frontier, and the strategic rationale behind the $4B Lumentum/Coherent investment announced almost exactly a year later.
The named NVIDIA supply chain is an equipment market roadmap. TSMC COUPE fabrication requires SoIC-X bumpless hybrid bonding tooling. Detachable optical sub-assembly integration requires precision fiber attach automation and MPO connector qualification. Liquid cooling co-design introduces thermal management tooling requirements. Fabrinet as systems integrator signals complex multi-component CPO module assembly moving to contract manufacturing at scale — a new opportunity category for advanced assembly equipment vendors beyond traditional semiconductor packaging.
Broadcom Validates 1 Million Flap-Free CPO Hours at Meta — First Hyperscale Production Reliability Proof Point
On October 1, 2025 — timed with ECOC 2025 in Copenhagen — Broadcom announced its CPO platform had accumulated one million cumulative 400G-equivalent port device hours of flap-free operation in Meta's high-temperature lab characterization environment, with zero link disruptions. The data was presented at ECOC 2025 as a formal paper: "Co-Packaged Optics Technology Evaluation for Hyperscale Data Center Fabric Switches." The platform tested was Broadcom's Gen-2 Tomahawk 5-Bailly chipset — the industry's first volume-production CPO solution. Alongside the flap-free result, testing showed 65% lower optics power versus pluggable modules. Near Margalit, VP/GM of Broadcom's Optical Systems Division, stated the milestone proves CPO "is not just a research concept — it is production-proven and ready to scale." Broadcom also confirmed its third-generation 200G/lane CPO platform is in development, with a fourth-generation (400G/lane) to follow.
The framing from the existing newsletter entry on Hock Tan's caution needs to be read alongside this result: Broadcom's engineering is running significantly ahead of its public messaging. A million port-hours at Meta, under high-temperature stress, in a facility running some of the world's largest AI training jobs, is effectively a hyperscale acceptance test. Link flapping in AI training clusters — where hundreds of thousands of GPUs execute synchronized computations — can abort entire job runs and waste massive compute cycles. Zero flaps across a million port-hours directly addresses the primary reliability objection to CPO deployment at scale, and substantially accelerates the decision timeline for other hyperscalers evaluating CPO transitions.
A million-hour zero-failure result under thermal stress establishes the floor for CPO qualification testing. It defines what test infrastructure must be capable of: high-temperature burn-in, link stability monitoring, and thermal cycling at module level — not just clean-room optical characterization. For test equipment vendors, this result sets the spec. Vendors who can deliver production-grade electro-optical burn-in at CPO module scale will be positioned to win qualification contracts at tier-1 OSATs and system integrators as Broadcom Bailly and its successors ramp.
Ayar Labs Raises $500M Series E at $3.75B Valuation — NVIDIA and AMD Re-Up as CPO Production Ramp Nears
Ayar Labs closed a $500 million Series E round on approximately March 4, 2026, led by Neuberger Berman and valuing the company at $3.75 billion — nearly four times its December 2024 valuation of $1 billion. The round brings Ayar's total funding to $870 million. New investors include ARK Invest, Insight Partners, MediaTek (which disclosed a $90 million contribution to Taiwanese regulators), Alchip Technologies, Qatar Investment Authority, Sequoia Global Equities, and 1789 Capital. Critically, strategic investors AMD Ventures and NVIDIA both re-committed capital, extending their participation from the December 2024 Series D. The round is structured with Neuberger Berman taking a board observer role and publicly signaling it views a near-term IPO as plausible. Pat Gelsinger (former Intel CEO, current Ayar board member) characterized the company as having addressed the core packaging and reliability challenges that previously blocked commercialization.
This follows Ayar's $155 million Series D closed December 11, 2024, which was the first round to draw AMD Ventures, Intel Capital, and NVIDIA as co-investors — a strategic signal that all three major GPU/XPU platform vendors were simultaneously endorsing Ayar's TeraPHY optical engine as the interconnect architecture for next-generation AI clusters. Ayar will deploy the Series E to scale high-volume production and test capacity, expand its Hsinchu, Taiwan office, and accelerate CPO deployment. TeraPHY and SuperNova laser modules are targeting high-volume production readiness by mid-2026. The timing of the Series E — immediately before NVIDIA's $4B Lumentum/Coherent announcement and GTC 2026 — created a compressed sequence of three major optical interconnect funding events within one week, representing the highest-density capital deployment period in CPO history.
Ayar's explicit use of proceeds for production scale-up and test capacity expansion is a direct equipment procurement signal. The Hsinchu office expansion positions Ayar within Taiwan's OSAT and advanced packaging ecosystem for TSMC COUPE-based integration. For test vendors, Ayar's TeraPHY chiplet architecture — stacked using SoIC-X, combining PIC + EIC + UCIe converter — requires multi-component electro-optical test at chiplet, module, and system levels. The scale of capital committed ($870M total) indicates this is no longer a pilot program.
Ayar Labs Integrates TeraPHY Into GUC's Advanced ASIC Packaging Workflow — CPO Enters the ASIC Design Services Pipeline
On November 16, 2025, Ayar Labs and Global Unichip Corp. (GUC) — TSMC's advanced ASIC design subsidiary and one of the highest-volume ASIC design service providers for hyperscalers globally — announced a strategic partnership to integrate Ayar's TeraPHY optical engines directly into GUC's advanced ASIC packaging and design workflow. This is qualitatively distinct from a component supply agreement: GUC is incorporating TeraPHY as a design primitive within its ASIC services offering, meaning that GUC's hyperscaler customers can now specify co-packaged optical I/O as a standard design option when contracting ASIC development. The collaboration is exploring CPO integration challenges in four domains — architectural, power and signal integrity, mechanical, and thermal — across GUC's full-service ASIC pipeline for AI, HPC, and networking applications.
The significance for the CPO ecosystem is architectural. GUC's position as TSMC's ASIC arm means that COUPE-qualified TeraPHY integration into GUC's workflow creates a direct pipeline from TSMC foundry process to hyperscaler-ready ASIC tape-out with CPO already designed in — removing one of the major friction points in CPO adoption, which has historically been the late-stage integration of optics into chip designs that were not originally architected for them. This partnership, combined with the September 2025 Alchip collaboration, makes Ayar the only CPO optical engine vendor with active integration agreements at both of Taiwan's leading high-complexity ASIC design service houses simultaneously.
GUC ASIC designs that include TeraPHY at the architectural stage will require CPO-aware test planning from the earliest design phases — not as a retrofit. This creates a pull-through demand for electro-optical wafer test, known-good-die verification, and fiber attach qualification within TSMC's CoWoS/COUPE assembly flow, at OSAT nodes that service GUC tapeouts. It directly expands the addressable market for CPO test infrastructure in Taiwan's OSAT ecosystem.
Lightmatter Reaches $4.4B Valuation, Ships Passage M1000 and L200, and Partners with GUC — The Other CPO Contender
Lightmatter is the highest-funded pure-play CPO startup not yet covered in this newsletter, and one of the most architecturally distinct. In October 2024, the company closed a $400 million Series D at a $4.4 billion valuation, led by T. Rowe Price with participation from Fidelity and GV (Google Ventures), bringing total funding to $850 million. On March 31, 2025, Lightmatter launched two products: the Passage M1000 Photonic Superchip — a 3D photonic interposer with 114 Tbps total optical bandwidth across a 4,000 mm² multi-reticle platform — and the Passage L200, the world's first 3D co-packaged optics product, available in 32 Tbps and 64 Tbps configurations (5–10x more than conventional CPO), targeting XPU and switch silicon integration with 2026 commercial availability. Both products manufacture through GlobalFoundries, with Lightmatter also developing TSMC COUPE integration. Assembly partners include ASE and Amkor for large-scale packaging complexes.
On January 26, 2026, Lightmatter and GUC (TSMC's ASIC design subsidiary) announced a strategic CPO partnership — the same partner Ayar Labs engaged in November 2025. Both Ayar and Lightmatter now have concurrent GUC relationships, which is significant: GUC has effectively become the primary ASIC design services gateway for CPO integration into hyperscaler ASIC workflows. Lightmatter also announced EDA tool integrations with Synopsys and Cadence on January 26–27, 2026, embedding Passage CPO interfaces into industry-standard chip design flows. Lightmatter's CEO Nick Harris has publicly stated he expects all next-generation GPUs designed for AI training and inference to be built on Passage, and targets product announcements with unnamed GPU/XPU partners in late 2027 for 2028 commercial availability. That timeline aligns directly with NVIDIA's projected NVLink CPO adoption window.
Lightmatter's 3D interposer approach — stacking EIC directly atop PIC within a single chiplet — creates packaging and test challenges distinct from TSMC COUPE's side-by-side integration. The M1000 multi-reticle platform (4,000 mm², larger than any single reticle) requires stitched-reticle wafer handling and multi-chip test that pushes ATE limits. GlobalFoundries and ASE as Lightmatter's manufacturing partners mean this CPO ecosystem runs largely parallel to the TSMC/COUPE ecosystem — creating a two-track CPO supply chain with different equipment implications for each track.
Marvell Acquires Celestial AI for Up to $5.5B — Photonic Fabric Enters the Scale-Up Race
Marvell Technology announced a definitive agreement to acquire Celestial AI on December 2, 2025, in a deal structured at $3.25 billion upfront with earnouts that could reach $5.5 billion if Celestial achieves $2 billion in cumulative revenue by the end of fiscal 2029. The acquisition brings Celestial's Photonic Fabric platform into Marvell's connectivity portfolio — a technology purpose-built for optical scale-up interconnect within and across racks, targeting package, system, and rack-level connections. Celestial claimed its platform delivers 16 Tbps bandwidth per chiplet with superior thermal stability compared to conventional CPO architectures, enabling deployment in high-density XPU environments that generate extreme heat.
The strategic read is significant. Marvell positions Celestial AI as the physical layer anchor for its UALink Consortium strategy, competing directly against NVIDIA's proprietary NVLink fabric and Broadcom's Bailly CPO platform. AWS VP Dave Brown endorsed the deal publicly, underscoring hyperscaler interest in an open-standard alternative for scale-up interconnect. For equipment strategists, the transaction signals that all-optical intra-rack connectivity is no longer speculative — it is now a funded, hyperscaler-validated product roadmap with a 2026–2029 commercialization horizon. The deal is expected to close in early 2026.
Photonic Fabric integration into custom AI accelerator packages will require assembly and test workflows distinct from conventional CPO. The claimed 25x bandwidth advantage and 10x latency improvement over current CPO alternatives implies a different integration architecture — likely chiplet-attach and optical I/O at the package level — creating new test cell requirements as production scales.
GlobalFoundries Acquires AMF and InfiniLink — Bids to Become Largest Pure-Play SiPho Foundry
GlobalFoundries executed two photonics acquisitions in November 2025 that together redefine its competitive position. On November 17–18, GF announced the acquisition of Advanced Micro Foundry (AMF), a Singapore-based silicon photonics foundry spun out of A*STAR's Institute of Microelectronics, and separately acquired InfiniLink, an Egypt-based startup designing optical transceiver chiplets that combine silicon photonics with analog mixed-signal components using advanced packaging. AMF adds over $75 million in projected 2026 revenue and extends GF's silicon photonics manufacturing from its Fab 8 facility in Malta, NY to a 200mm platform in Singapore, providing supply chain resilience across two geographies. GF projects annual silicon photonics revenue exceeding $1 billion by 2030. Plans include a silicon photonics R&D Center of Excellence in Singapore, in partnership with A*STAR.
InfiniLink's iOTC (integrated optical transceiver chiplet) technology provides an end-to-end design capability complementing AMF's manufacturing, giving GF both process and IP for pluggable and CPO roadmaps. Combined with PsiQuantum's ongoing Omega chipset production at GF's Fab 8, GF is now the foundry most deeply embedded in both CPO and photonic quantum supply chains simultaneously — a rare dual-domain position.
AMF's 200mm Singapore platform is separate from GF's 300mm New York operation. As GF scales both sites for CPO production, OSATs and test equipment vendors must address multi-geography, multi-wafer-size qualification — expanding the serviceable equipment market but also increasing complexity for vendors without flexible platforms.
AMD Acquires Enosemi; Ciena Buys Nubis — M&A Wave Consolidates Silicon Photonics IP
AMD acquired Silicon Valley startup Enosemi in May 2025, bringing in-house a team with a track record of shipping photonic integrated circuits in volume. Enosemi had previously worked with AMD as an external photonics partner and fabricated chipsets via GlobalFoundries. AMD framed the acquisition as a direct enabler of its CPO and photonics solutions across next-generation AI systems — an explicit signal that AMD intends to compete not just in GPU silicon but in full-stack optical interconnect for AI clusters. Financial terms were not disclosed.
Separately, Ciena acquired Nubis Communications — a developer of optical silicon photonics technology — for $270 million in late 2025. GlobalFoundries also acquired InfiniLink (see story above) in the same period. Together, these moves represent a structural consolidation wave: established OEMs and foundries are absorbing the most commercially viable silicon photonics startups before the CPO ramp enters full volume. The window for independent SiPho IP vendors is narrowing.
As hyperscalers and chip OEMs bring SiPho design in-house, the test and assembly equipment market will increasingly serve captive production lines rather than independent module makers. This shifts competitive dynamics toward long-term OEM partnerships over open-market sales — and places a premium on vendors with prior qualification inside AMD, Marvell, or Broadcom supply chains.
TSMC COUPE Becomes the Dominant CPO Platform — Broadcom Joins NVIDIA in Adoption
TSMC's COUPE (Compact Universal Photonic Engine) platform has emerged as the de facto foundry integration standard for production-intent CPO. Built on TSMC's SoIC-X bumpless hybrid bonding technology, COUPE stacks an electrical integrated circuit (EIC) directly on top of a photonic IC (PIC) at sub-10 micron pitch, minimizing impedance at the die-to-die interface. NVIDIA's Spectrum-X Photonics and Quantum-X Photonics switch platforms — unveiled at GTC 2025 — are the first COUPE products to ship, targeting 1.6 Tbps per optical engine. At SEMICON Taiwan 2025 in September, TSMC confirmed CPO mass production on track for 2026, with COUPE integration into CoWoS packaging as the next milestone. The roadmap extends to 6.4 Tbps and 12.8 Tbps optical engines via interposer-level integration.
Critically, Broadcom has now committed to COUPE for its future switch and custom accelerator roadmaps — abandoning its prior Fan-Out Wafer-Level Packaging (FOWLP) approach developed with SPIL, which analysts note cannot scale beyond 100G per lane due to parasitic capacitance constraints. Ayar Labs has also added COUPE to its roadmap alongside GlobalFoundries' Fotonix platform. TSMC filed approximately 50 silicon photonics-related U.S. patents in 2024, roughly double Intel's rate, consolidating its IP position in a domain where it previously lagged GlobalFoundries and Tower Semiconductor.
COUPE's SoIC-X hybrid bonding architecture requires wafer bonding equipment, ultra-precise alignment, and double-sided electro-optical testing capability. As Broadcom transitions production to COUPE, the OSAT and test ecosystem must qualify for COUPE-specific workflows — a meaningful opportunity for ficonTEC, Teradyne, and COHU, and a potential displacement risk for vendors whose tools were optimized for FOWLP-style integration.
Ayar Labs Closes Three Strategic Partnerships — Ecosystem Infrastructure for CPO Scale
Ayar Labs executed three significant partnerships between September and November 2025, collectively representing the most active CPO ecosystem-building period for any single company in the coverage window. In September, Ayar and Alchip Technologies announced a strategic partnership combining Ayar's TeraPHY optical engine chiplets with Alchip's advanced packaging expertise and TSMC's process technology, targeting AI scale-up infrastructure for hyperscalers. In November, Ayar announced a second partnership with Global Unichip Corp. (GUC), integrating TeraPHY optical engines into GUC's advanced ASIC design services — enabling CPO to enter GUC's workflow for AI, HPC, and networking chip customers. Ayar also opened a new Taiwan office and doubled its San Jose headquarters in this period, signaling manufacturing readiness ambitions rather than continued lab-scale activity.
Separately, POET Technologies and Sivers Semiconductors announced a collaboration in September 2025 to develop External Light Source (ELS) modules for CPO, targeting what Northland Capital Markets estimated as a $1 billion-plus annual ELS market opportunity. Early prototypes are expected in the first half of 2026, with production readiness by year-end. The ELS segment is increasingly recognized as a critical CPO sub-system, as most production architectures keep laser sources external to the heat-generating ASIC for reliability and redundancy reasons.
GUC and Alchip are two of Taiwan's most active ASIC design service providers for hyperscalers. Their CPO integration with Ayar's TeraPHY creates a commercial pipeline for volume CPO-enabled ASICs into the TSMC CoWoS/COUPE supply chain — which will in turn require EO wafer-level test, fiber attachment, and CPO module assembly infrastructure at OSAT scale in Taiwan.
STMicroelectronics Enters High-Volume SiPho Production on 300mm — Plans to Quadruple by 2027
STMicroelectronics announced on March 9, 2026 — immediately ahead of OFC — that it has entered high-volume production for its PIC100 silicon photonics platform on 300mm wafer lines, supplying leading hyperscalers with 800G and 1.6T optical transceivers. ST plans to more than quadruple production capacity by 2027 with further expansion in 2028, backed by customer capacity reservations. LightCounting CEO Vladimir Kozlov characterized ST's move as a demonstration of the capabilities needed to provide hyperscalers with secure long-term supply and manufacturing resilience, projecting the silicon photonics market above $34 billion by 2030 with CPO contributing over $9 billion by that year.
ST simultaneously unveiled its PIC100 TSV roadmap — a next-generation platform integrating through-silicon via technology to increase optical connectivity density and thermal efficiency, designed to support future generations of NPO and CPO for hyperscalers' long-term migration toward deeper optical-electronic integration. ST will present a first demonstration of a 1.6T-DR8 silicon photonics transceiver engine at OFC 2026, developed jointly with Sicoya.
ST entering high-volume production on 300mm for hyperscalers is a leading indicator that silicon photonics test capacity must scale commensurately. ST's PIC100 TSV roadmap is particularly relevant: TSV integration in photonic platforms introduces additional test complexity at the wafer level, expanding the scope of electro-optical wafer probe requirements beyond what current double-sided systems address.
Teradyne + ficonTEC Launch Industry's First High-Volume Double-Sided SiPho Wafer Test Cell
Teradyne and ficonTEC announced the availability of the first high-volume, double-sided wafer probe test cell for silicon photonics on March 31, 2025, timed for OFC 2025. The system integrates Teradyne's UltraFLEXplus ATE and IG-XL programming environment with ficonTEC's optical alignment, probing, and wafer handling technologies, enabling production-environment testing of hybrid bonded PIC/EIC wafers — the exact wafer configuration used in TSMC's COUPE architecture. The partnership addresses known-good-die testing before dicing and packaging into CPO devices or pluggable transceivers, a critical yield gate as production volumes scale.
In June 2025, ficonTEC extended this ecosystem with the launch of an ATE-agnostic, single-sided electro-optical wafer-level tester — fully compatible with both Teradyne's UltraFLEXplus and Advantest architectures — giving chip manufacturers and foundries a complete test suite covering both sides of hybrid bonded photonic wafers under a unified software interface. ficonTEC's installed base of over 1,400 systems worldwide, combined with Teradyne's market breadth, positions this partnership as the early production standard for CPO wafer test. Teradyne separately acquired Quantifi Photonics in early 2025 to add PIC test instrument capability to its portfolio.
This is the clearest equipment market signal of the coverage period: a tier-1 ATE supplier and a leading photonics automation vendor have jointly qualified and shipped the first production-intent CPO wafer test system. The timing — ahead of TSMC COUPE volume ramp in 2026 — positions Teradyne and ficonTEC favorably with OSAT customers in Taiwan qualifying COUPE-based workflows. The open-ecosystem commitment by Teradyne (supporting multiple prober and alignment vendors) is a deliberate competitive posture against a potential proprietary lock-in from pure photonics test specialists.
Broadcom CEO Signals CPO Caution — But Bailly Platform Commitment Holds
In December 2025, Broadcom CEO Hock Tan publicly expressed caution about the near-term deployment timeline for silicon photonics and CPO, stating the industry is "not quite there yet." This was notable given Broadcom's simultaneous transition to TSMC COUPE for its future switch ASICs (abandoning the FOWLP approach developed with SPIL). The apparent contradiction is best read as Tan managing customer expectations on deployment timing — likely 2027 for volume CPO-based switching — while the engineering and foundry commitments to COUPE are proceeding on schedule. IDTechEx's December 2025 CPO market report forecasts a 37% CAGR from 2026 to over $20 billion by 2036, with Broadcom's Bailly platform as one of the two dominant ecosystem anchors alongside NVIDIA's COUPE-based switches. Analyst consensus holds that CPO in switch ASICs is a 2026–2027 volume event despite Tan's tempering language.
Tan's public caution is a timing signal, not a commitment reversal. Equipment vendors should expect Broadcom's CPO qualification activity to proceed on engineering timelines while commercial ramp announcements lag. For OSATs and test vendors, this means qualification pipeline activity remains active even if high-volume PO acceleration is 6–12 months behind the most optimistic forecasts.
Google Willow Achieves Below-Threshold Quantum Error Correction — First Chip to Suppress Errors as Qubits Scale
On December 9, 2024, Google Quantum AI published results in Nature announcing Willow, a 105-qubit superconducting processor that became the first quantum chip to demonstrate below-threshold quantum error correction — meaning error rates decrease, rather than increase, as the number of physical qubits scales up. This "below threshold" regime had been a theoretical goal pursued for nearly 30 years. In its benchmark test, Willow completed a random circuit sampling (RCS) task in under five minutes that would take today's fastest supercomputers an estimated 10²⁵ years by Google's calculation. On October 22, 2025, Google extended this with the Quantum Echoes announcement — the first verifiable quantum advantage on hardware for a real algorithmic task (the out-of-order time correlator), running 13,000x faster on Willow than the best classical algorithm on a top supercomputer. Willow is manufactured in Google Quantum AI's own facility at UC Santa Barbara. The team has roughly 300 people and operates its own state-of-the-art fab.
Important context: the demonstrated logical error rates (~0.14% per cycle) remain many orders of magnitude above the ~10⁻⁶ levels required for industrially useful fault-tolerant algorithms. Demonstrations remain limited to quantum memory and synthetic benchmarks — no large-scale commercial algorithms have been demonstrated. The RCS benchmark is specifically designed to be hard for classical computers but does not correspond to commercially useful computation. The below-threshold result is nonetheless a genuine architectural advance that changes the scaling roadmap for superconducting qubit systems and provides the field's first experimental confirmation that surface code error correction can work in practice as qubit counts grow.
Google's vertically integrated model — design, fabrication, and test under one roof at UCSB — is the reference for superconducting qubit production at research-to-scale transition. The tooling requirements (Josephson junction deposition, cryogenic packaging, dilution refrigerator test infrastructure) are established and increasingly well understood. As Willow's successor generations target larger qubit arrays and lower error floors, the volume of chips required for fault-tolerant demonstrations will begin to stress Google's current fab capacity, creating a potential opening for external foundry and packaging services.
Microsoft Majorana 1 — World's First Topological Qubit QPU, Designed to Scale to 1 Million Qubits on a Single Chip
On February 19, 2025, Microsoft announced Majorana 1, the world's first QPU powered by a Topological Core: an 8-qubit chip built from topoconductors (indium arsenide + aluminum heterostructures) that create Majorana zero modes — quasiparticles that store quantum information at the ends of superconducting nanowires. The topological protection is hardware-level, theorized to reduce error correction overhead approximately 10-fold versus conventional approaches, enabling a path to one million qubits on a single chip. A peer-reviewed paper appeared simultaneously in Nature. Microsoft is one of two companies selected by DARPA for the final phase of the US2QC (Underexplored Systems for Utility-Scale Quantum Computing) benchmarking program. CEO Satya Nadella called the timeline for a useful fault-tolerant quantum computer "years, not decades." Microsoft's largest quantum lab is at Lyngby, Denmark (expanded in 2025); a second system, Magne, combining Microsoft's error correction with Atom Computing neutral-atom hardware, is under construction for Denmark's QuNorth initiative with operations expected by late 2026.
Scientific dispute is material here: a critique published in Nature on March 7, 2025, cast doubt on the topological gap protocol underpinning Microsoft's claim to have created working topological qubits, and community skepticism has grown. Microsoft has not yet provided additional empirical data in response. Because topological qubits are Microsoft's sole qubit strategy — they have no superconducting or trapped-ion fallback — validation of the underlying physics is existential for the program. The manufacturing implications (InAs/Al epitaxial nanowire fabrication at atomic precision) are a distinct tooling set from all other qubit modalities, and the equipment market for this approach remains conditional on scientific validation being upheld. This story requires ongoing tracking.
If the topological approach is validated, the fabrication implications are unprecedented: compound semiconductor heterostructures at atomic-scale precision (InAs/Al), not achievable in standard silicon CMOS fabs. The equipment set resembles III-V compound semiconductor manufacturing more than silicon photonics or superconducting qubit fab. The 10x reduction in error correction overhead, if realized, means dramatically fewer physical qubits per logical qubit — a fundamentally different yield economics model. DARPA US2QC program milestones are the key signal to track for equipment demand timing.
Quantinuum Raises $600M at $10B Valuation; Files Confidential S-1 — Sector's Largest Quantum IPO in Pipeline
On September 4, 2025, Honeywell announced a $600 million equity raise for Quantinuum at a $10 billion pre-money valuation — doubling its $5 billion valuation from January 2024 and marking the largest single financing round in quantum computing to that date. The round included NVIDIA's NVentures, Quanta Computer, QED Investors, JPMorgan Chase (re-investing), Mitsui, Amgen, Cambridge Quantum Holdings, and Serendipity Capital. Capital is earmarked for the launch of Helios, Quantinuum's next-generation H-Series quantum computer (announced November 5, 2025), expected to support at least 10 highly reliable logical qubits and bring the system below the error correction threshold for a wider set of codes. On January 14, 2026, Honeywell announced Quantinuum's confidential submission of a Form S-1 draft registration statement to the SEC — the formal start of the IPO process, with reports targeting a $20 billion+ valuation. This would be the largest quantum computing company to go public and the sector's first major pure-play quantum IPO.
Quantinuum holds consistently the world's highest-performing trapped-ion quantum computer by published fidelity metrics. Its QCCD (Quantum Charge-Coupled Device) architecture achieved best-in-class two-qubit gate fidelities and was the platform in the landmark Microsoft/Quantinuum logical qubit collaboration demonstrating 800x error rate reduction on logical vs. physical circuits. The IPO pipeline — alongside PsiQuantum, Infleqtion, and PASQAL — signals that the sector's first generation of hardware companies is approaching public capital markets in a compressed timeframe, with major implications for how production-scale manufacturing gets funded. Honeywell itself is separating into three public companies by 2H 2026, with Quantinuum as a key asset in the value unlock thesis.
Quantinuum's trapped-ion QCCD architecture requires microfabricated ion trap chips — patterned ceramic and silicon substrates with precision electrodes, integrated photonics for laser delivery, and vacuum packaging. As the H-Series scales from current qubit counts toward hundreds of logical qubits, trap chip fabrication becomes a volume manufacturing challenge the field has not yet faced at commercial scale. IPO-level capital and NVIDIA investment signal commercial production intent within a 2–4 year window. Quantinuum's trap chip foundry relationships (currently largely in-house) will become a strategic decision point as scale demands grow.
PsiQuantum Raises $1 Billion Series E — Photonic Quantum Manufacturing at GlobalFoundries Enters Utility Scale
PsiQuantum closed a $1 billion Series E round on September 10, 2025, led by BlackRock with participation from Temasek, Baillie Gifford, Macquarie Capital, Ribbit Capital, the Qatar Investment Authority, and NVIDIA's venture arm NVentures, among others. The round valued PsiQuantum at $7 billion. Alongside the fundraising, PsiQuantum announced a new collaboration with NVIDIA spanning quantum algorithms, software, GPU-QPU integration, and its silicon photonics platform. The company will use proceeds to break ground on utility-scale quantum computing sites in Brisbane, Australia, and Chicago — and to scale production of its Omega quantum photonic chipset, manufactured at GlobalFoundries' Fab 8 in Malta, NY.
The Omega chipset integrates high-performance single-photon sources, superconducting single-photon detectors, and a barium titanate (BTO)-enabled electro-optic switch — the latter described as the previously missing component for scaling optical quantum computing. PsiQuantum manufactures BTO at its California facility before integrating with GlobalFoundries' silicon photonics wafers. The company's thesis — that fault-tolerant quantum computing requires approximately one million physical qubits and that photonic qubits fabricated in a commercial semiconductor foundry provide the most scalable path — makes PsiQuantum the most manufacturing-infrastructure-mature quantum hardware company in the sector as of this coverage period.
PsiQuantum's 127,000 sq. ft. Test & Assembly facility near San Jose is operational and supporting intermediate-scale system development. The BTO-enabled optical switch is a proprietary electro-optic component with its own specialized fabrication and characterization requirements — distinct from conventional SiPho test workflows. As utility-scale sites in Brisbane and Chicago break ground, assembly and test at quantum system level will require cryogenic integration and optical packaging infrastructure that does not yet exist at commercial scale.
IonQ Acquires Oxford Ionics for $1.075B — Semiconductor-Chip Trapped Ion Comes Under One Roof
IonQ announced the acquisition of Oxford Ionics, a UK-based trapped-ion quantum computing company, on June 9, 2025, in a deal valued at approximately $1.075 billion ($1.065B in stock plus $10M cash). The transaction closed on September 17, 2025, following UK government clearance under the National Security and Investment Act — with conditions requiring Oxford Ionics' hardware, staff, IP, and manufacturing capacity to remain in Britain and be available for independent government assessment. Oxford Ionics' key differentiation is its use of standard semiconductor chip manufacturing to produce ion trap qubit systems — a manufacturing-compatible approach that aligns IonQ's roadmap with commercial semiconductor processes rather than custom fabrication. The combined entity targets delivery of systems with 256 physical qubits at 99.99% fidelity by 2026, and IonQ's long-term roadmap calls for 2 million qubits by 2030.
The acquisition follows a broader IonQ consolidation strategy: the company also completed acquisitions of Qubitekk (quantum networking), Lightsynq Technologies (quantum memory), ID Quantique (quantum-safe cryptography), and Capella Space during 2024–2025, building one of the most diversified quantum hardware and networking portfolios of any public company. IonQ's cash position reached approximately $1.6 billion following an additional $1 billion equity raise in 2025.
Oxford Ionics' semiconductor-chip-based ion trap approach is significant for equipment vendors: it implies that trapped-ion quantum hardware can increasingly be produced using existing semiconductor fabrication infrastructure rather than entirely bespoke tools. However, the UK government's hardware-retention conditions create a geographically bifurcated production footprint (UK hardware, US software/networking) that complicates single-facility manufacturing scale-up strategies.
IBM Unveils Nighthawk Processor and Loon Architecture — Quantum Advantage Targeted for End of 2026
At its annual Quantum Developer Conference on November 12, 2025, IBM unveiled IBM Quantum Nighthawk, its most advanced quantum processor to date. Nighthawk features 120 qubits connected by 218 next-generation tunable couplers in a square lattice, a 20%+ increase in coupler density compared to the prior Heron processor, enabling circuits with 30% greater complexity at low error rates. IBM targets delivery to users by end of 2025, with future Nighthawk iterations expected to support up to 7,500 two-qubit gates by end of 2026 and 10,000 by 2027. IBM framed Nighthawk as designed to deliver "quantum advantage" — the point at which a quantum computer can outperform all classical methods on a meaningful problem — by the end of 2026.
In parallel, IBM announced IBM Quantum Loon, an experimental processor that demonstrates all key components needed for fault-tolerant quantum computing, including multi-layer high-quality low-loss routing for long on-chip connections (c-couplers) and qubit reset between computations. IBM's full fault-tolerant roadmap targets its Quantum Starling system in 2029, featuring 200 logical qubits capable of executing 100 million error-corrected operations — a system-level specification, not just a qubit count target.
IBM's 2026 quantum advantage claim implies that the company views current fabrication and control systems as sufficient for a commercially meaningful milestone — a signal that quantum hardware manufacturing at the level of 120–200 qubits is now repeatable enough to be the basis for competitive claims. For equipment vendors, the Loon architecture's c-coupler and multi-layer routing innovations represent new fabrication complexity requirements that will cascade into process control and metrology tool demand.
Neutral Atom Platforms Cross Into Level-2 Error Correction — QuEra and Microsoft/Atom Computing Deliver First Customer Systems
IEEE Spectrum reported in January 2026 that neutral atom quantum computers are on track to become the first modality to deliver "Level 2" quantum systems — machines implementing robust error-correction protocols — to paying customers in 2026. QuEra has delivered an error-correction-capable machine to Japan's National Institute of Advanced Industrial Science and Technology (AIST), with plans to make it available to global customers in 2026. Microsoft and Atom Computing jointly plan to deliver an error-corrected quantum computer to the Export and Investment Fund of Denmark and the Novo Nordisk Foundation — explicitly described as targeting scientific advantage rather than commercial advantage, but positioned as the first step toward that transition.
The neutral atom modality is gaining attention because it achieves high qubit fidelity using laser-controlled atoms in optical tweezers — a platform that, unlike superconducting qubits, does not require dilution refrigerators operating at millikelvin temperatures, simplifying some facility requirements while creating different laser and vacuum system manufacturing demands. PASQAL (neutral atoms, France) and Atom Computing are the other active neutral atom vendors moving toward customer delivery in 2026.
Neutral atom system delivery at the error-correction level represents a transition point for quantum hardware manufacturing: systems must now be reproducible enough to be shipped to external customers and operated reliably outside the originating lab. This implies increasing demand for specialized test, calibration, and qualification tooling for neutral atom platforms — a pre-commercial but emerging equipment opportunity distinct from the superconducting qubit ecosystem.
Quantum Sector Raises $3.77B in Nine Months — Investment Pace More Than Doubles Year-Over-Year
The quantum computing sector raised over $1.25 billion in Q1 2025 alone — more than double the $550 million raised in Q1 2024 — and cumulative equity funding through September 2025 reached $3.77 billion, a dramatic acceleration from prior years. The funding landscape has shifted from venture capital dominance toward a hybrid model combining private investment with expanding government commitments. The U.S. Department of Energy's Quantum Leadership Act of 2025, introduced in February 2025, proposes $2.5 billion in quantum funding across fiscal years 2026–2030. Separately, New Mexico and DARPA jointly committed $240 million for the Quantum Frontier Project through 2029.
Multiple quantum companies are advancing toward public market listings: Infleqtion is merging with Churchill Capital Corp X at a $1.8 billion valuation; Horizon Quantum Computing is merging with dMY Squared (NYSE: DMYY) in a Q1 2026 close; and PsiQuantum, Quantinuum, and PASQAL are reported to be preparing for future listings. The structural dynamic — rising capital, widening government commitment, and approaching public market events — indicates that 2026 will see increased pressure on quantum hardware companies to demonstrate manufacturing repeatability as an investor-facing credibility signal, not only as a technical milestone.
The surge in quantum funding is creating demand for specialized quantum manufacturing infrastructure in advance of commercialization. Equipment vendors who can provide cryogenic assembly, dilution refrigerator integration, and quantum chip characterization tools are entering a market that is well-capitalized but still pre-production at scale. Average funding round size of $28.6M across the sector suggests most companies are in infrastructure build-out stages — exactly the phase where capital equipment purchasing decisions are made.
Tower Semiconductor Deepens Quantum Photonics Manufacturing — Xanadu, Salience Labs Partnerships Announced
Tower Semiconductor made two quantum-relevant foundry partnership announcements in February 2026. On February 19, Tower and Xanadu deepened their strategic collaboration to accelerate photonic quantum hardware innovation — strengthening the manufacturing foundation for commercial-scale photonic quantum computing using Tower's silicon photonics platform. On February 25, Tower and Salience Labs announced a partnership to manufacture at-scale optical circuit switches for next-generation AI data centers using Salience's innovative switch architecture on Tower's differentiated SiPho platforms. Tower is presenting both silicon photonics and quantum computing applications at OFC 2026, positioning itself as a foundry serving both the CPO AI infrastructure market and the photonic quantum hardware market — the only major pure-play analog foundry currently doing so with public customer relationships in both domains.
Tower's silicon photonics platform also supports DWDM lasers (via the Scintil Photonics collaboration announced February 17, 2026), optical circuit switching, and FMCW LiDARs for physical AI — building a broad photonic platform that straddles AI infrastructure and quantum applications. This dual positioning mirrors the strategic dual-domain value proposition that GlobalFoundries is pursuing following its AMF and InfiniLink acquisitions.
Tower's role as a foundry for both CPO and quantum photonic hardware on the same SiPho platform creates an important equipment qualification precedent: process tools validated for AI-grade photonic circuits may increasingly be applicable — with appropriate adaptation — to quantum photonic chip fabrication. This convergence, if it deepens, could allow equipment vendors to address both markets from a single process tool investment rather than requiring separate quantum-specific tool development.
CPO Market: IDTechEx (Dec 2025) forecasts 37% CAGR, CPO market exceeding $20B by 2036. LightCounting projects silicon photonics market above $34B by 2030, with CPO contributing over $9B. ResearchAndMarkets (Jan 2026) cites volume production beginning 2026–2027. Analyst ranges reflect genuine variance in CPO deployment timing; Broadcom CEO's public caution is a data point, not consensus.
Quantum Market: SpinQ data shows global quantum computing market at $1.8B–$3.5B in 2025, projecting $5.3B by 2029 at 32.7% CAGR. More aggressive forecasts (McKinsey, BCG) place the broader quantum technology opportunity at $97B by 2035 and $850B economic value by 2040. Wide variance across analyst forecasts reflects genuine commercial uncertainty — quantum hardware remains pre-commercial at scale as of this edition.